/***********************************************************************/
/*                                                                     */
/*  FILE        :vecttbl.c                                             */
/*  DATE        :Thu, Aug 04, 2011                                     */
/*  DESCRIPTION :Initialize of Vector Table                            */
/*  CPU TYPE    :SH7254R                                               */
/*                                                                     */
/*  This file is generated by Renesas Project Generator (Ver.4.18).    */
/*  NOTE:THIS IS A TYPICAL EXAMPLE.                                    */
/***********************************************************************/
/*********************************************************************
*
* Device     : SH2A-FPU/SH7254R
*
* File Name  : vecttbl.c
*
* Abstract   : Initialize of Vector Table.
*
* History    : 1.00  (2009-01-13)  [Hardware Manual Revision : 1.00]
*
* Copyright(c) 2009 Renesas Technology Corp.
*               And Renesas Solutions Corp.,All Rights Reserved. 
*
*********************************************************************/
#include "vecttbl.h"

#pragma section = ".inttable"
__root const APP_INTTABLE_ELEM  __vector_table[] @ ".inttable" = 
{
  // 4 Illegal code
  Dummy,
  // 5 Reserved
  Dummy,
  // 6 Illegal slot
  Dummy,
  // 7 Reserved
  Dummy,
  // 8 Reserved
  Dummy,
  // 9 CPU Address error
  _iar_program_start,
  // 10 DMAC Address error
  _iar_program_start,
  // 11 NMI
  Dummy,
  // 12 User breakpoint trap
  Dummy,
  // 13 Reserved
  Dummy,
  // 14 H-UDI
  Dummy,
  // 15 Register bank over
  _iar_program_start,
  // 16 Register bank under
  _iar_program_start,
  // 17 ZERO_DIV
  Dummy,
  // 18 OVER_DIV
  Dummy,
  // 19 Reserved
  Dummy,
  // 20 Reserved
  Dummy,
  // 21 Reserved
  Dummy,
  // 22 Reserved
  Dummy,
  // 23 Reserved
  Dummy,
  // 24 Reserved
  Dummy,
  // 25 Reserved
  Dummy,
  // 26 Reserved
  Dummy,
  // 27 Reserved
  Dummy,
  // 28 Reserved
  Dummy,
  // 29 Reserved
  Dummy,
  // 30 Reserved
  Dummy,
  // 31 Reserved
  Dummy,
  // 32 TRAPA (User Vecter)
  Dummy,
  // 33 TRAPA (User Vecter)
  OSCtxSw,
  // 34 TRAPA (User Vecter)
  Dummy,
  // 35 TRAPA (User Vecter)
  Dummy,
  // 36 TRAPA (User Vecter)
  Dummy,
  // 37 TRAPA (User Vecter)
  Dummy,
  // 38 TRAPA (User Vecter)
  Dummy,
  // 39 TRAPA (User Vecter)
  Dummy,
  // 40 TRAPA (User Vecter)
  Dummy,
  // 41 TRAPA (User Vecter)
  Dummy,
  // 42 TRAPA (User Vecter)
  Dummy,
  // 43 TRAPA (User Vecter)
  Dummy,
  // 44 TRAPA (User Vecter)
  Dummy,
  // 45 TRAPA (User Vecter)
  Dummy,
  // 46 TRAPA (User Vecter)
  Dummy,
  // 47 TRAPA (User Vecter)
  Dummy,
  // 48 TRAPA (User Vecter)
  Dummy,
  // 49 TRAPA (User Vecter)
  Dummy,
  // 50 TRAPA (User Vecter)
  Dummy,
  // 51 TRAPA (User Vecter)
  Dummy,
  // 52 TRAPA (User Vecter)
  Dummy,
  // 53 TRAPA (User Vecter)
  Dummy,
  // 54 TRAPA (User Vecter)
  Dummy,
  // 55 TRAPA (User Vecter)
  Dummy,
  // 56 TRAPA (User Vecter)
  Dummy,
  // 57 TRAPA (User Vecter)
  Dummy,
  // 58 TRAPA (User Vecter)
  Dummy,
  // 59 TRAPA (User Vecter)
  Dummy,
  // 60 TRAPA (User Vecter)
  Dummy,
  // 61 TRAPA (User Vecter)
  Dummy,
  // 62 TRAPA (User Vecter)
  Dummy,
  // 63 TRAPA (User Vecter)
  Dummy,
  // 64 Interrupt IRQ0
  Dummy,
  // 65 Interrupt IRQ1
  Dummy,
  // 66 Interrupt IRQ2
  Dummy,
  // 67 Interrupt IRQ3
  Dummy,
  // 68 Interrupt IRQ4
  Dummy,
  // 69 Interrupt IRQ5
  Dummy,
  // 70 Interrupt IRQ6
  Dummy,
  // 71 Interrupt IRQ7
  Dummy,
  // 72 Reserved
  Dummy,
  // 73 Reserved
  Dummy,
  // 74 Reserved
  Dummy,
  // 75 Reserved
  Dummy,
  // 76 Reserved
  Dummy,
  // 77 Reserved
  Dummy,
  // 78 Reserved
  Dummy,
  // 79 Reserved
  Dummy,
  // 80 Interrupt PINT0
  Dummy,
  // 81 Interrupt PINT1
  Dummy,
  // 82 Interrupt PINT2
  Dummy,
  // 83 Interrupt PINT3
  Dummy,
  // 84 Interrupt PINT4
  Dummy,
  // 85 Interrupt PINT5
  Dummy,
  // 86 Interrupt PINT6
  Dummy,
  // 87 Interrupt PINT7
  Dummy,
  // 88 Reserved
  Dummy,
  // 89 Reserved
  Dummy,
  // 90 Reserved
  Dummy,
  // 91 ROM FIFE
  Dummy,
  // 92 A/D ADI0
  Dummy,
  // 93 Reserved
  Dummy,
  // 94 Reserved
  Dummy,
  // 95 Reserved
  Dummy,
  // 96 A/D ADI1
  Dummy,
  // 97 Reserved
  Dummy,
  // 98 Reserved
  Dummy,
  // 99 Reserved
  Dummy,
  // 100 Reserved
  Dummy,
  // 101 Reserved
  Dummy,
  // 102 Reserved
  Dummy,
  // 103 Reserved
  Dummy,
  // 104 RCANET0 ERS_0
  Dummy,
  // 105 RCANET0 OVR_0
  Dummy,
  // 106 RCANET0 RM01_0
  Dummy,
  // 107 RCANET0 SLE_0
  Dummy,
  // 108 DMAC0 DEI0
  Dummy,
  // 109 DMAC0 HEI0
  Dummy,
  // 110 Reserved
  Dummy,
  // 111 Reserved
  Dummy,
  // 112 DMAC1 DEI1
  Dummy,
  // 113 DMAC1 HEI1
  Dummy,
  // 114 Reserved
  Dummy,
  // 115 Reserved
  Dummy,
  // 116 DMAC2 DEI2
  Dummy,
  // 117 DMAC2 HEI2
  Dummy,
  // 118 Reserved
  Dummy,
  // 119 Reserved
  Dummy,
  // 120 DMAC3 DEI3
  Dummy,
  // 121 DMAC3 HEI3
  Dummy,
  // 122 Reserved
  Dummy,
  // 123 Reserved
  Dummy,
  // 124 DMAC4 DEI4
  Dummy,
  // 125 DMAC4 HEI4
  Dummy,
  // 126 Reserved
  Dummy,
  // 127 Reserved
  Dummy,
  // 128 DMAC5 DEI5
  Dummy,
  // 129 DMAC5 HEI5
  Dummy,
  // 130 Reserved
  Dummy,
  // 131 Reserved
  Dummy,
  // 132 DMAC6 DEI6
  Dummy,
  // 133 DMAC6 HEI6
  Dummy,
  // 134 Reserved
  Dummy,
  // 135 Reserved
  Dummy,
  // 136 DMAC7 DEI7
  Dummy,
  // 137 DMAC7 HEI7
  Dummy,
  // 138 Reserved
  Dummy,
  // 139 Reserved
  Dummy,
  // 140 CMT CMI0
  OSTickISR,
  // 141 Reserved
  Dummy,
  // 142 Reserved
  Dummy,
  // 143 Reserved
  Dummy,
  // 144 CMT CMI1
  Dummy,
  // 145 Reserved
  Dummy,
  // 146 Reserved
  Dummy,
  // 147 Reserved
  Dummy,
  // 148 BSC CMTI
  Dummy,
  // 149 Reserved
  Dummy,
  // 150 USB EP4FULL
  Dummy,
  // 151 USB EP5EMPTY
  Dummy,
  // 152 WDT ITI
  Dummy,
  // 153 E-DMAC EINT0
  Dummy,
  // 154 USB EP1FULL
  Dummy,
  // 155 USB EP2EMPTY
  Dummy,
  // 156 MTU2 MTU0 TGI0A
  Dummy,
  // 157 MTU2 MTU0 TGI0B
  Dummy,
  // 158 MTU2 MTU0 TGI0C
  Dummy,
  // 159 MTU2 MTU0 TGI0D
  Dummy,
  // 160 MTU2 MTU0 TGI0V
  Dummy,
  // 161 MTU2 MTU0 TGI0E
  Dummy,
  // 162 MTU2 MTU0 TGI0F
  Dummy,
  // 163 Reserved
  Dummy,
  // 164 MTU2 MTU1 TGI1A
  Dummy,
  // 165 MTU2 MTU1 TGI1B
  Dummy,
  // 166 Reserved 
  Dummy,
  // 167 Reserved
  Dummy,
  // 168 MTU2 MTU1 TGI1V
  Dummy,
  // 169 MTU2 MTU1 TGI1U
  Dummy,
  // 170 Reserved 
  Dummy,
  // 171 Reserved
  Dummy,
  // 172 MTU2 MTU2 TGI2A
  Dummy,
  // 173 MTU2 MTU2 TGI2B
  Dummy,
  // 174 Reserved 
  Dummy,
  // 175 Reserved
  Dummy,
  // 176 MTU2 MTU2 TGI2V
  Dummy,
  // 177 MTU2 MTU2 TGI2U
  Dummy,
  // 178 Reserved 
  Dummy,
  // 179 Reserved
  Dummy,
  // 180 MTU2 MTU3 TGI3A
  Dummy,
  // 181 MTU2 MTU3 TGI3B
  Dummy,
  // 182 MTU2 MTU3 TGI3C
  Dummy,
  // 183 MTU2 MTU3 TGI3D
  Dummy,
  // 184 MTU2 MTU3 TGI3V
  Dummy,
  // 185 Reserved 
  Dummy,
  // 186 Reserved
  Dummy,
  // 187 Reserved 
  Dummy,
  // 188 MTU2 MTU4 TGI4A
  Dummy,
  // 189 MTU2 MTU4 TGI4B
  Dummy,
  // 190 MTU2 MTU4 TGI4C
  Dummy,
  // 191 MTU2 MTU4 TGI4D
  Dummy,
  // 192 MTU2 MTU4 TGI4V
  Dummy,
  // 193 Reserved 
  Dummy,
  // 194 Reserved
  Dummy,
  // 195 Reserved 
  Dummy,
  // 196 MTU2 MTU5 TGI5U
  Dummy,
  // 197 MTU2 MTU5 TGI5V
  Dummy,
  // 198 MTU2 MTU5 TGI5W
  Dummy,
  // 199 Reserved 
  Dummy,
  // 200 POE2 OEI1
  Dummy,
  // 201 POE2 OEI2 
  Dummy,
  // 202 Reserved 
  Dummy,
  // 203 Reserved
  Dummy,
  // 204 MTU2S MTU3S TGI3A 
  Dummy,
  // 205 MTU2S MTU3S TGI3B
  Dummy,
  // 206 MTU2S MTU3S TGI3C
  Dummy,
  // 207 MTU2S MTU3S TGI3D 
  Dummy,
  // 208 MTU2S MTU3S TGI3V
  Dummy,
  // 209 Reserved 
  Dummy,
  // 210 Reserved 
  Dummy,
  // 211 Reserved
  Dummy,
  // 212 MTU2S MTU4S TGI4A 
  Dummy,
  // 213 MTU2S MTU4S TGI4B 
  Dummy,
  // 214 MTU2S MTU4S TGI4C 
  Dummy,
  // 215 MTU2S MTU4S TGI4D 
  Dummy,
  // 216 MTU2S MTU4S TGI4V 
  Dummy,
  // 217 Reserved 
  Dummy,
  // 218 Reserved
  Dummy,
  // 219 Reserved 
  Dummy,
  // 220 MTU2S MTU5S TGI5U 
  Dummy,
  // 221 MTU2S MTU5S TGI5V
  Dummy,
  // 222 MTU2S MTU5S TGI5W 
  Dummy,
  // 223 Reserved
  Dummy,
  // 224 POE2 OEI3
  Dummy,
  // 225 Reserved
  Dummy,
  // 226 USB USI0 
  Dummy,
  // 227 USB USI1 
  Dummy,
  // 228 IIC3 STPI
  Dummy,
  // 229 IIC3 NAKI 
  Dummy,
  // 230 IIC3 RXI 
  Dummy,
  // 231 IIC3 TXI
  Dummy,
  // 232 IIC3 TEI 
  Dummy,
  // 233 RSPI SPERI 
  Dummy,
  // 234 RSPI SPRXI 
  Dummy,
  // 235 RSPI SPTXI
  Dummy,
  // 236 SCI SCI4 ERI4 
  Dummy,
  // 237 SCI SCI4 RXI4 
  Dummy,
  // 238 SCI SCI4 TXI4
  Dummy,
  // 239 SCI SCI4 TEI4 
  Dummy,
  // 240 SCI SCI0 ERI0
  Dummy,
  // 241 SCI SCI0 RXI0
  Dummy,
  // 242 SCI SCI0 TXI0
  Dummy,
  // 243 SCI SCI0 TEI0
  Dummy,
  // 244 SCI SCI1 ERI1
  Dummy,
  // 245 SCI SCI1 RXI1
  Dummy,
  // 246 SCI SCI1 TXI1
  Dummy,
  // 247 SCI SCI1 TEI1
  Dummy,
  // 248 SCI SCI2 ERI2
  Dummy,
  // 249 SCI SCI2 RXI2
  Dummy,
  // 250 SCI SCI2 TXI2
  Dummy,
  // 251 SCI SCI2 TEI2
  Dummy,
  // 252 SCIF SCIF3 BRI3
  Dummy,
  // 253 SCIF SCIF3 ERI3
  Dummy,
  // 254 SCIF SCIF3 RXI3
  Dummy,
  // 255 SCIF SCIF3 TXI3
  Dummy,
  // xx Reserved
  Dummy
};

void Dummy(void){/* sleep(); */}